The present invention relates to a signal transmitting circuit and method. More particularly, it relates to an improved signal transmitting circuit and method for use in a memory circuit or microprocessor which transmits in parallel a large number of signals in synchronization with a given clock inside one semiconductor chip or between two semiconductor chips.
Conventional microprocessors or memory circuits for processing signals in parallel, such as an image memory, a synchronous dynamic random-access memory (SDRAM), and a static random-access memory (SRAM), have adopted the following basic structure for driving signal lines, i.e., for transmitting signals.
FIG. 24 illustrates the basic structure, in which are shown: signal lines 100 and 101 each composed of a single wire; drivers 102 and 103 each composed of, e.g., an inverter for transmitting signals to the above respective signal lines; and receivers 104 and 105 each composed of, e.g., an inverter for receiving signals from the respective signal lines.
A description will be given to the operation of the above conventional structure with reference to FIG. 25. In the case of transmitting parallel signals in synchronization with a clock MCLK, an input is latched on the rising edge or falling edge (rising edge in FIG. 25) of the above clock MCLK, while the drivers 102 and 103 are simultaneously activated to drive the respective signals 100 and 101. The signals on the above respective signal lines 100 and 101 are latched into the inputs of the respective receivers 104 and 105 on the rising edge or falling edge (rising edge in the drawing) of the clock MCLK, while the receivers 104 and 105 are simultaneously activated, thereby detecting the signals on the signal lines.
In the above conventional structure, however, since each of the signal lines 100 and 101 is composed of a single wire, information as a signal on the signal line is represented by a potential difference between the potential of each of the signal lines after a level shift and the reference threshold voltage of the corresponding receiver for discerning a signal. Consequently, the potential amplitude of each of the signal lines should be sufficiently large, in consideration of power-source noise or the like, so that a large amount of power is consumed to transmit signals. In addition, the signal transmission is greatly influenced by a wiring delay determined by the product of the wiring capacitance of each of the signal lines and the resistance thereof. Hence, the above conventional structure has the disadvantageous of high power consumption, in spite of its low-speed operation.
To eliminate the disadvantage, there has been adopted a conventional structure in which other signal lines equal in number to the signal lines 100 and 101 are provided to perform differential signal transmission, whereby signals on the respective signal lines are differentially transmitted between the respective signal lines and the corresponding other signal lines.
However, although it is possible to achieve power saving since the potential amplitude of each of the signal lines can be reduced in the structure, the number of signal lines is increased, so that when the number of parallel bits is increased to, e.g., "64" or "128" in an image memory or the like, the chip area and cost are increased disadvantageously. Therefore, the structure is not applicable to a circuit aimed at miniaturization and low cost.